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74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
Rev. 01 -- 18 October 2004 Product data sheet
1. General description
The 74LVC1G175 is a high-performance, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using Ioff. The Ioff circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. The 74LVC1G175 is a single positive edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q output. The master reset (MR) is an asynchronous active LOW input and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock transition, for predictable operation. Schmitt-trigger action at all inputs makes the circuit highly tolerant to slower input rise and fall times.
2. Features
s s s s Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant inputs for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: x JESD8-7 (1.65 V to 1.95 V) x JESD8-5 (2.3 V to 2.7 V) x JESD8B/JESD36 (2.7 V to 3.6 V). 24 mA output drive (VCC = 3.0 V) ESD protection: x HBM EIA/JESD22-A114-B exceeds 2000 V x MM EIA/JESD22-A115-A exceeds 200 V. CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels Inputs accept voltages up to 5 V Multiple package options Specified from -40 C to +85 C and -40 C to +125 C.
s s
s s s s s s
Philips Semiconductors
74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
3. Quick reference data
Table 1: Quick reference data GND = 0 V; Tamb = 25 C; tr = tf 2.5 ns. Symbol Parameter Conditions CL = 50 pF; VCC = 3.3 V CL = 50 pF; VCC = 3.3 V CL = 50 pF; VCC = 3.3 V Min 1.0 1.0 175 VCC = 3.3 V
[1] [2]
Typ 3.1 2.5 300 2.5 14
Max 5.7 5.8 -
Unit ns ns MHz pF pF
tPHL, tPLH propagation delay CP to Q propagation delay MR to Q fmax CI CPD
[1]
maximum clock frequency input capacitance power dissipation capacitance
-
CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi x N + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = number of inputs switching; (CL x VCC2 x fo) = sum of the outputs. The condition is VI = GND to VCC.
[2]
4. Ordering information
Table 2: Ordering information Package Temperature range Name 74LVC1G175GW 74LVC1G175GV 74LVC1G175GM -40 C to +125 C -40 C to +125 C -40 C to +125 C SC-88 SC-74 XSON6 Description plastic surface mounted package; 6 leads plastic surface mounted package; 6 leads plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm Version SOT363 SOT457 SOT886 Type number
5. Functional diagram
6 1 3 MR D FF 1 CP
001aaa469
C1 1D R 4
3 Q 4 6
001aaa468
Fig 1. Logic symbol.
Fig 2. IEC logic symbol.
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Product data sheet
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Philips Semiconductors
74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
CP
C C C C
Q
C D C MR
C
C
C
C
001aaa466
Fig 3. Logic diagram.
6. Pinning information
6.1 Pinning
175
CP 1 6 MR CP 1 6 MR
GND
2
175
5
VCC
GND
2
5
VCC
D
3
001aaa467
4
Q
D
3
4
Q
001aab657
Transparent top view
Fig 4. Pin configuration SC-88 and SC-74.
Fig 5. Pin configuration XSON6.
6.2 Pin description
Table 3: Symbol CP GND D Q VCC MR Pin description Pin 1 2 3 4 5 6 Description clock input (LOW-to-HIGH, edge-triggered) ground (0 V) data input flip-flop output supply voltage master reset input (active LOW)
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Product data sheet
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Philips Semiconductors
74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
7. Functional description
7.1 Function table
Table 4: Function table [1] Input MR Reset (clear) Load `1' Load `0'
[1]
Operating mode
Output CP X D X h l Q L H L
L H H
H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition; = LOW-to-HIGH CP transition; X = don't care.
8. Limiting values
Table 5: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK VI IOK VO IO ICC, IGND Tstg Ptot
[1] [2]
Parameter supply voltage input diode current input voltage output diode current output voltage output diode current VCC or GND current storage temperature power dissipation
Conditions VI < 0 V
[1]
Min -0.5 -0.5 [1] [2] [1] [2]
Max +6.5 -50 +6.5 50 +6.5 50 100 +150 250
Unit V mA V mA V mA mA C mW
VO > VCC or VO < 0 V active mode Power-down mode VO = 0 V to VCC
-0.5 -0.5 -65
VCC + 0.5 V
Tamb = -40 C to +125 C
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed. When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
9. Recommended operating conditions
Table 6: Symbol VCC VI VO Recommended operating conditions Parameter supply voltage input voltage output voltage active mode Power-down mode; VCC = 0 V Conditions Min 1.65 0 0 0 Max 5.5 5.5 VCC 5.5 Unit V V V V
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Product data sheet
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Philips Semiconductors
74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
Recommended operating conditions ...continued Parameter ambient temperature input rise and fall times VCC = 1.65 V to 2.7 V VCC = 2.7 V to 5.5 V Conditions Min -40 0 0 Max +125 20 10 Unit C ns/V ns/V
Table 6: Symbol Tamb tr, tf
10. Static characteristics
Table 7: Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = -40 C to +85 VIH C [1] 0.65 x VCC 1.7 2.0 0.7 x VCC VCC - 0.1 1.2 1.9 2.2 2.3 3.8 1.54 2.15 2.50 2.62 4.11 0.07 0.12 0.17 0.33 0.39 0.1 0.1 0.1 5 2.5 0.7 0.8 0.3 x VCC 0.10 0.45 0.30 0.40 0.55 0.55 5 10 10 500 V V V V V V V V V V V V V V V V V V V A A A A pF VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V VIL LOW-level input voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V VOH HIGH-level output voltage VI = VIH or VIL IO = -100 A; VCC = 1.65 V to 5.5 V IO = -4 mA; VCC = 1.65 V IO = -8 mA; VCC = 2.3 V IO = -12 mA; VCC = 2.7 V IO = -24 mA; VCC = 3.0 V IO = -32 mA; VCC = 4.5 V VOL LOW-level output voltage VI = VIH or VIL IO = 100 A; VCC = 1.65 V to 5.5 V IO = 4 mA; VCC = 1.65 V IO = 8 mA; VCC = 2.3 V IO = 12 mA; VCC = 2.7 V IO = 24 mA; VCC = 3.0 V IO = 32 mA; VCC = 4.5 V ILI Ioff ICC ICC CI input leakage current power OFF leakage current VI = 5.5 V or GND; VCC = 5.5 V VI or VO = 5.5 V; VCC = 0 V Conditions Min Typ Max Unit
HIGH-level input voltage VCC = 1.65 V to 1.95 V
0.35 x VCC V
quiescent supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V additional quiescent supply current per pin input capacitance VI = VCC - 0.6 V; IO = 0 A; VCC = 2.3 V to 5.5 V
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Product data sheet
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Philips Semiconductors
74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
Table 7: Static characteristics ...continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = -40 C to +125 C VIH HIGH-level input voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V VIL LOW-level input voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V VOH HIGH-level output voltage VI = VIH or VIL IO = -100 A; VCC = 1.65 V to 5.5 V IO = -4 mA; VCC = 1.65 V IO = -8 mA; VCC = 2.3 V IO = -12 mA; VCC = 2.7 V IO = -24 mA; VCC = 3.0 V IO = -32 mA; VCC = 4.5 V VOL LOW-level output voltage VI = VIH or VIL IO = 100 A; VCC = 1.65 V to 5.5 V IO = 4 mA; VCC = 1.65 V IO = 8 mA; VCC = 2.3 V IO = 12 mA; VCC = 2.7 V IO = 24 mA; VCC = 3.0 V IO = 32 mA; VCC = 4.5 V ILI Ioff ICC ICC input leakage current power OFF leakage current VI = 5.5 V or GND; VCC = 5.5 V VI or VO = 5.5 V; VCC = 0 V 0.10 0.70 0.45 0.60 0.80 0.80 20 20 40 5000 V V V V V V A A A A VCC - 0.1 0.95 1.7 1.9 2.0 3.4 V V V V V V 0.65 x VCC 1.7 2.0 0.7 x VCC 0.7 0.8 0.3 x VCC V V V V V V V Conditions Min Typ Max Unit
0.35 x VCC V
quiescent supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V additional quiescent supply current per pin VI = VCC - 0.6 V; IO = 0 A; VCC = 2.3 V to 5.5 V
[1]
All typical values are measured at Tamb = 25 C.
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Product data sheet
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Philips Semiconductors
74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
11. Dynamic characteristics
Table 8: Dynamic characteristics GND = 0 V; see Figure 8 Symbol tPHL, tPLH Parameter C [1] see Figure 6 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V propagation delay MR to Q see Figure 7 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V tW clock pulse width HIGH or LOW see Figure 6 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V master reset pulse width LOW see Figure 7 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V trem removal time master reset see Figure 7 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V tsu set-up time D to CP see Figure 6 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V
[2] [2] [2] [2] [2] [2]
Conditions
Min
Typ
Max
Unit
Tamb = -40 C to +85
propagation delay CP to Q
1.5 1.0 1.0 1.0 1.0 1.5 1.0 1.0 1.0 1.0 6.2 2.7 2.7 2.7 2.0 6.2 2.7 2.7 2.7 2.0 1.9 1.4 1.3 1.2 1.0 2.9 1.7 1.7 1.3 1.1
4.9 3.1 3.2 3.1 2.2 4.3 2.8 3.0 2.5 2.0 1.3 1.6 0.4 0.5 -
13.4 7.1 7.1 5.7 4.0 12.9 7.0 7.0 5.8 4.1 -
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Product data sheet
Rev. 01 -- 18 October 2004
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Philips Semiconductors
74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
Table 8: Dynamic characteristics ...continued GND = 0 V; see Figure 8 Symbol th Parameter hold time D to CP Conditions see Figure 6 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V fmax maximum clock pulse frequency see Figure 6 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V CPD power dissipation capacitance propagation delay CP to Q VCC = 3.3 V
[3] [4] [2] [2]
Min 0.0 0.3 0.5 1.2 0.5 80 175 175 175 200 -
Typ 0.2 125 300 14
Max -
Unit ns ns ns ns ns MHz MHz MHz MHz MHz pF
Tamb = -40 C to +125 C tPHL, tPLH see Figure 6 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V propagation delay MR to Q see Figure 7 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V tW clock pulse width HIGH or LOW see Figure 6 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V master reset pulse width LOW see Figure 7 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V 6.2 2.7 2.7 2.7 2.0 ns ns ns ns ns 6.2 2.7 2.7 2.7 2.0 ns ns ns ns ns 1.5 1.0 1.0 0.5 0.5 17 9.0 9.0 7.5 5.5 ns ns ns ns ns 1.5 1.0 1.0 0.5 0.5 17 9.0 9.0 7.5 5.5 ns ns ns ns ns
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Product data sheet
Rev. 01 -- 18 October 2004
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Philips Semiconductors
74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
Table 8: Dynamic characteristics ...continued GND = 0 V; see Figure 8 Symbol trem Parameter removal time master reset Conditions see Figure 7 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V tsu set-up time D to CP see Figure 6 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V th hold time D to CP see Figure 6 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V fmax maximum clock pulse frequency see Figure 6 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V
[1] [2] [3] All typical values are measured at Tamb = 25 C. These typical values are measured at VCC = 3.3 V. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi x N + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = number of inputs switching; (CL x VCC2 x fo) = sum of the outputs. The condition is VI = GND to VCC.
Min 1.9 1.4 1.3 1.2 1.0 2.9 1.7 1.7 1.3 1.1 0.0 0.3 0.5 1.2 0.5 80 175 175 175 200
Typ -
Max -
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz MHz MHz
[4]
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Product data sheet
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Philips Semiconductors
74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
12. Waveforms
VI D input GND th tsu 1/fmax VI CP input GND tW tPHL VOH Q output VOL VM
001aaa465
VM
th tsu
VM
tPLH
Measurement points are given in Table 9. The shaded areas indicate when the input is permitted to change for predictable output performance. VOL and VOH are typical output voltage drop that occur with the output load.
Fig 6. The clock input (CP) to output (Q) propagation delays, the clock pulse width, the D to CP set-up, the CP to D hold times and the maximum clock pulse frequency. Table 9: VCC 1.65 V to 1.95 V 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V 4.5 V to 5.5 V Measurement points Output VM 0.5 x VCC 0.5 x VCC 1.5 V 1.5 V 0.5 x VCC Input VM 0.5 x VCC 0.5 x VCC 1.5 V 1.5 V 0.5 x VCC VI VCC VCC 2.7 V 2.7 V VCC tr = tf 2.0 ns 2.0 ns 2.5 ns 2.5 ns 2.5 ns
Supply voltage
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Product data sheet
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Philips Semiconductors
74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
VI MR input GND tW VI CP input GND t PHL VOH Q output VOL VM
001aaa464
VM
t rem
VM
Measurement points are given in Table 9. VOL and VOH are typical output voltage drop that occur with the output load.
Fig 7. The master reset (MR) input to output (Q) propagation delays, the master reset pulse width and the MR to CP removal time.
VEXT VCC PULSE GENERATOR VI D.U.T. RT CL RL VO RL
mna616
Test data is given in Table 10. Definitions for test circuit: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig 8. Load circuitry for switching times. Table 10: VCC 1.65 V to 1.95 V 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V 4.5 V to 5.5 V Test data Input VI VCC VCC 2.7 V 2.7 V VCC Load CL 30 pF 30 pF 50 pF 50 pF 50 pF RL 1 k 500 500 500 500 VEXT tPLH, tPHL open open open open open tPZH, tPHZ GND GND GND GND GND tPZL, tPLZ 2 x VCC 2 x VCC 6V 6V 2 x VCC
Supply voltage
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Product data sheet
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74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
13. Package outline
Plastic surface mounted package; 6 leads SOT363
D
B
E
A
X
y
HE
vMA
6
5
4
Q
pin 1 index
A
A1
1
e1 e
2
bp
3
wM B detail X Lp
c
0
1 scale
2 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.8 A1 max 0.1 bp 0.30 0.20 c 0.25 0.10 D 2.2 1.8 E 1.35 1.15 e 1.3 e1 0.65 HE 2.2 2.0 Lp 0.45 0.15 Q 0.25 0.15 v 0.2 w 0.2 y 0.1
OUTLINE VERSION SOT363
REFERENCES IEC JEDEC EIAJ SC-88
EUROPEAN PROJECTION
ISSUE DATE 97-02-28
Fig 9. Package outline SOT363 (SC-88).
9397 750 13762 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 -- 18 October 2004
12 of 17
Philips Semiconductors
74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
Plastic surface mounted package; 6 leads
SOT457
D
B
E
A
X
y
HE
vMA
6
5
4
Q
pin 1 index
A A1 c
1
2
3
Lp
e
bp
wM B detail X
0
1 scale
2 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.9 A1 0.1 0.013 bp 0.40 0.25 c 0.26 0.10 D 3.1 2.7 E 1.7 1.3 e 0.95 HE 3.0 2.5 Lp 0.6 0.2 Q 0.33 0.23 v 0.2 w 0.2 y 0.1
OUTLINE VERSION SOT457
REFERENCES IEC JEDEC EIAJ SC-74
EUROPEAN PROJECTION
ISSUE DATE 97-02-28 01-05-04
Fig 10. Package outline SOT457 (SC-74).
9397 750 13762 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 -- 18 October 2004
13 of 17
Philips Semiconductors
74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm
SOT886
b 1 2 3 4x L1 L
(2)
e
6 e1
5 e1
4
6x
(2)
A
A1 D
E
terminal 1 index area 0 DIMENSIONS (mm are the original dimensions) UNIT mm A (1) max 0.5 A1 max 0.04 b 0.25 0.17 D 1.5 1.4 E 1.05 0.95 e 0.6 e1 0.5 L 0.35 0.27 L1 0.40 0.32 1 scale 2 mm
Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION SOT886 REFERENCES IEC JEDEC MO-252 JEITA EUROPEAN PROJECTION ISSUE DATE 04-07-15 04-07-22
Fig 11. Package outline SOT886 (XSON6).
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Product data sheet
Rev. 01 -- 18 October 2004
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Philips Semiconductors
74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
14. Revision history
Table 11: Revision history Release date 20041018 Data sheet status Product data sheet Product data sheet Change notice Doc. number 9397 750 13762 9397 750 12973 Supersedes 74LVC1G175_1 Document ID 74LVC1G175_2 Modifications 74LVC1G175_1
*
Package outline. Marking code and ESD data added.
20040318
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Product data sheet
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74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
15. Data sheet status
Level I II Data sheet status [1] Objective data Preliminary data Product status [2] [3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
III
Product data
Production
[1] [2] [3]
Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
16. Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
17. Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
18. Contact information
For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
9397 750 13762
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 -- 18 October 2004
16 of 17
Philips Semiconductors
74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
19. Contents
1 2 3 4 5 6 6.1 6.2 7 7.1 8 9 10 11 12 13 14 15 16 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 16 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Contact information . . . . . . . . . . . . . . . . . . . . 16
(c) Koninklijke Philips Electronics N.V. 2004
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 18 October 2004 Document number: 9397 750 13762
Published in The Netherlands

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